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    • 专利摘要:
    The invention relates to a method for manufacturing a semiconductor structure, characterized in that the method comprises a step of depositing (201) a crystalline passivation layer continuously covering the entire surface of a layer based on element nitride III, said crystalline passivation layer deposited from a precursor containing silicon atoms is composed of silicon atoms bonded to the surface of the III element nitride layer and arranged according to a periodic arrangement so that a diffraction pattern of said passivation crystalline layer obtained by graft incidence electron diffraction in the [1-100] direction comprises: - two non-integer order diffraction lines (0, - 1/3) and (0, -2/3) between the central line (0, 0) and the integer line (0, -1), and - two non-integer order diffraction lines (0 , 1/3) and (0, 2/3) between the central line (0, 0) and the complete line of order r (0, 1).
    公开号:FR3031833A1
    申请号:FR1550461
    申请日:2015-01-21
    公开日:2016-07-22
    发明作者:Fabrice Semond；Jean Massies；Eric Frayssinet
    申请人:Centre National de la Recherche Scientifique CNRS；
    IPC主号:
    专利说明:

    [0001] FIELD OF THE INVENTION The invention relates to a method for manufacturing a semiconductor structure based on elemental nitrides. III and such a semiconductor structure. PRESENTATION OF THE PRIOR ART The semiconductor materials based on nitrides of elements III of the periodic table - such as materials based on gallium nitride GaN - occupy an increasingly important place in the fields of electronics. and optoelectronics, especially for the manufacture of light-emitting diodes. Existing processes for fabricating a III nitride semiconductor structure, such as gallium nitride GaN on a substrate, for example silicon or sapphire, generally result in a high through-dislocation density. related to the difference in mesh parameter between the host zo substrate and the element III nitride semiconductor materials. These through dislocations are particularly disadvantageous in the case of semiconductor structures forming light emitting devices based on element III nitride semiconductor materials since the through dislocations increase the leakage currents and deteriorate the efficiency of the luminescence of these light emitting devices. Three-dimensional epitaxial techniques - such as epitaxial lateral overgrowth (ELO), pendeo-epitaxy from nano-pillars, addition of antisurfactant species, modification of growth conditions have proven effective in reducing the density of through dislocations in element III nitride semiconductor materials. The approach used by these techniques to reduce the density of through dislocations is to initiate a three-dimensional (island) growth mode, and then to promote island coalescence to obtain a two-dimensional layer of gallium nitride GaN. A popular in-situ technique for reducing through-hole dislocation density is to insert an interlayer of silicon nitride SiNx below the GaN layer. More specifically, a silicon nitride SiNx layer is deposited in situ on a layer of element III nitride, then a layer of gallium nitride GaN is deposited on the SiNx silicon nitride layer. This technique has proven to be effective in reducing through-hole dislocation density for conventional c-plane GaN but also for semi-non-polar orientations. It is recognized that a surface treatment based on silicon and ammonia leads to the formation of a nano-porous layer of silicon nitride SiNx which acts as a nano-mask for initiating a three-dimensional growth mode of GaN. The growth of GaN is inhibited in the regions where the SiNx silicon nitride is located. On the other hand growth occurs in the nano-pores, that is to say in the openings of the nano-mask. The density and the size of these are controlled by the silicon nitride SiNx deposition time and their distribution on the surface is random. For example, the following documents deal with these topics: The article entitled "A New Method of Reducing Dislocation Density in GaN Layer Grown on Sapphire Substrate by MOVPE" by Sakai et al., J. Cryst. Growth, 221, 334 (2000), the article entitled "Anti-Surfactant in III-Nitride Epitaxy - Quantum Dot Formation and Dislocation Termination" by S. Tanaka et al., Jap. J. Appl. Phys., 39, L83 1 (2000), the article "Efficacy of single and double SiNx interlayers on defect reduction in GaN overlayers grown by organometallic vapor-phase epitaxy", by F. Yun et al., J. Appl. Phys., 98, 123502 (2005), the patent application DE10151092 A1, the patent application WO2007 / 133603 A2.
    [0002] It has recently been shown that this type of treatment can also lead to the formation of a crystalline structure noted 3112x3112 R300, particularly in the article "Blocking Growth by Electrically Active Subsurface Layer: The Effects of Si as an Antisurfactant in the Growth of GaN ", by T. Markurt et al. Physical Review Letters 110, 036103 (2013). In this article, the crystalline layer is manufactured so as to obtain a partially covered surface, with greater or less uncovered regions that are called "openings" and this layer is called "nanoporous". During the deposition step of the gallium nitride GaN layer, the epitaxial gallium nitride preferentially grows in the apertures of the nanoporous layer so as to form islands. Once the islands are formed, the growth parameters are adjusted so that the gallium nitride GaN develops laterally so as to cover the SiNx covered areas, and coalesce to form a gallium nitride GaN layer (3D growth). The growth of the gallium nitride layer is then continued until a desired thickness of gallium nitride GaN (2D growth) is obtained. The coalescence thickness of gallium nitride GaN is defined as the thickness required to obtain a fully coalesced GaN layer after insertion of the SiNx layer. The reader will have understood that the increase in the duration of the surface treatment, and therefore the amount of SiNx deposited, has the effect of increasing the coverage rate of the SiNx layer and thus to reduce the density of nitride islands. of gallium GaN, which makes it possible to reduce the density of passing dislocations. On the other hand, the lower the gallium nitride islet density GaN, the greater the GaN gallium plating thickness required to achieve coalescence. It is therefore particularly advantageous to determine the optimum coverage rate of the SiNx layer to make such a process exploitable industrially. In addition, the existing processes for manufacturing GaN-based devices on a substrate generally comprise a first step of depositing a buffer layer, which may be, for example, aluminum nitride AIN for a silicum substrate possibly followed by a step of depositing a layer of AlGaN aluminum and gallium nitride on the aluminum nitride buffer layer AlN. The nano-mask can then be deposited on the AlN or AlGaN layer. Other methods include using a sapphire substrate and depositing a layer of GaN at a low temperature as a buffer layer, in which case the nano-mask is deposited on the GaN buffer layer. A disadvantage of the growth technique with the nano-mask of SiNx mentioned relates to the fact that oxidation reactions can take place on the surface of the buffer layer not covered by the SiNx layer. In particular, the buffer layer can oxidize at the openings in the event of exposure to air of the substrate consisting of the substrate, the buffer layer and the SiNx layer. Therefore, in the methods of the state of the art, the GaN (or final) gallium nitride layer is formed on the SiNx layer immediately after the formation thereof, with no possibility of storage of the support prior to deposition. a layer of gallium nitride thereon. Another disadvantage of this technique is that there is no way to define the optimal duration of the deposition step of the nanoporous SiNx layer. This optimal duration, related to the size of the openings and their density, varies according to the starting substrate used for growth, the type of reactor used for growth, and other parameters such as concentrations of gaseous precursors, etc. The size of the openings and their density are non-measurable quantities, therefore the determination of the optimal duration of the deposition step of the nanoporous layer of SiNx can only be obtained empirically by carrying out successive tests which must be repeated at whenever one of the growth parameters (ie substrate, reactor, etc.) is modified, which is costly in time and, above all, does not make it possible to carry out a generic process, that is to say generally applicable .
    [0003] An object of the present invention is to provide a method for overcoming at least one of the aforementioned drawbacks.
    [0004] SUMMARY OF THE INVENTION To this end, the invention provides a method of manufacturing a semiconductor structure, characterized in that the method comprises a step of depositing a crystalline passivation layer continuously covering the entire surface of the substrate. a nitride-based layer of elements III of the semiconductor structure, said crystalline passivation layer being deposited from a precursor containing silicon atoms and said crystalline passivation layer being composed of silicon atoms bound to the surface of the nitride layer of elements III and arranged in a periodic arrangement so that a diffraction image of said crystalline passivation layer obtained by electron diffraction grazing incidence in the direction [1-100] comprises: - a central line (0, 0) and lines of integer order (0, -1) and (0, 1), - two diffraction lines of non-integer order (0, -1/3) and (0, -2/3) in be the central line (0, 0) and the line of integer order (0, -1), and - two diffraction lines of non-integer order (0, 1/3) and (0, 2/3) between the central line (0, 0) and the line of integer order (0, 1). The fact of depositing a crystalline layer which covers the entire surface of a zo layer based on element III nitrides of the semiconductor structure allows to completely passivate the surface of this layer based on element III nitrides. and therefore prevent any oxidation reaction thereof. This makes it possible to store the semiconductor structure covered with the crystalline passivation layer prior to deposition of additional layers of the element III nitride semiconductor structure. Furthermore, the deposition of the crystalline layer which covers the entire surface makes it possible to dispense with the empirical phases of development and optimization of the processes of the prior art based on a step of deposition of a nanoporous layer Of SiNx, in particular the determination of the optimum size of the nanopores as well as the optimum density of the nanopores. The step of depositing a crystalline silicon-based passivation layer further allows a subsequent growth of a crystalline layer thereon, for example a III-nitride-based layer, while a nanoporous amorphous layer covering the element III nitride layer would not allow this subsequent growth. The diffraction pattern described corresponds to a rotated hexagonal periodic arrangement of 300 with respect to the lattice of the III nitride-based layer and of the mesh parameter - / / "§ § times greater than the mesh parameter of the III nitride-based layer network, which makes it possible to promote this subsequent growth of a crystalline layer, It will be understood below that when a layer A is mentioned as being on a layer B, that layer It may be directly on the B layer, or may be located above the B layer and separated from said B layer by one or more intermediate layers, It will also be understood that when a layer A is mentioned as being on a layer B, it may cover the entire surface of the layer B, or a portion of said layer B. Preferred but non-limiting aspects of the device according to the invention are the following: the crystalline layer of passivation near a simple periodicity in the crystallographic direction [1-210] so that a diffraction pattern of said passivation crystalline layer obtained by graft incidence electron diffraction in the [1-210] direction has a central line (0 , 0) and lines of integer order (0, -1) and (0, 1) without any non-integer order lines between them; Said crystalline passivation layer consists of silicon atoms bonded to the surface of the nitride layer of elements III and arranged in a hexagonal periodic arrangement rotated by 30 ° with respect to the network of the nitride layer. III elements and with a mesh parameter .Nr§ times greater than the mesh parameter of the network of the element III nitride-based layer; The step of depositing the crystalline passivation layer consists of an ultra-vacuum deposition - the step of depositing the crystalline passivation layer consists of a deposition by molecular beam epitaxy; the method comprises a step of measuring the degree of coverage of the crystalline passivation layer by electron diffraction at grazing incidence in the crystallographic direction [1-100] during the step of depositing the crystalline passivation layer so as to obtaining a diffraction pattern of said crystalline passivation layer, wherein the duration of the step of depositing the crystalline passivation layer is a function of the intensity of at least one non-integer order diffraction line of this diffraction pattern of the crystalline passivation layer obtained by electron diffraction in the [1-100] direction; the diffraction pattern of the crystalline layer comprises in the direction [1-100]: a central line (0, 0) and lines of integer order (0, -1) and (0, 1), - two diffraction lines of non-integer order (0, -1/3) and (0, -2/3) between the central line (0, 0) and the line of integer order (0, -1) and two non-integer (0, 1/3) and (0, 2/3) diffraction patterns between the center line (0, 0) and the integer line (0, 1) The step of depositing the crystalline passivation layer being interrupted when the luminous intensity of said non-integer order lines is maximum; the step of depositing the crystalline passivation layer consists of a vapor phase deposition; the step of depositing the crystalline passivation layer consists of an organometallic vapor phase deposition; the crystalline passivation layer has a thickness of less than 6 A; the method comprises a step of forming on a substrate a buffer layer, said buffer layer comprising the element-based nitride layer III on which the crystallization passivation layer is deposited; The buffer layer has, at the end of its formation, a thickness of between 10 and 200 nm; the substrate is based on silicon and the step of forming the buffer layer includes the deposition of a layer of aluminum nitride AIN; the step of forming the buffer layer includes depositing a layer of aluminum gallium nitride and AlGaN on the aluminum nitride layer. The invention also relates to a semiconductor structure based on element III nitrides comprising a layer based on element III nitrides, all of a surface of which is totally covered by a crystalline passivation layer comprising silicon atoms. bound to the surface and arranged in a periodic arrangement such that a diffraction pattern of said passivation crystalline layer obtained by graft incidence electron diffraction in the [1-100] direction comprises: - a central line (0 , 0) and lines of integer order (0, -1) and (0, 1), - two diffraction lines of non-integer order (0, -1/3) and (0, -2/3 ) between the central line (0, 0) and the line of integer order (0, -1), and - two diffraction lines of non-integer order (0, 1/3) and (0, 2/3 ) between the central line (0, 0) and the line of integer order (0, 1). Preferred but non-limiting aspects of the structure according to the invention are as follows: the crystalline layer has a simple periodicity in the crystallographic direction [1-120] so that a diffraction image of said crystalline passivation layer obtained by electron diffraction grazing incidence in the direction [1-210] comprises a central line (0, 0) and lines of integer order (0, -1) and (0, 1) without lines of non order between them; said crystalline passivation layer consists of silicon atoms bonded to the surface of the nitride layer of elements III and arranged in a hexagonal periodic arrangement rotated 30 ° with respect to the network of the layer based on element nitride III and with a mesh parameter, rs times larger than the mesh parameter of the network of the element III nitride layer; The crystalline passivation layer has a thickness of less than 6 Å; the nitride-based layer of elements III is a self-supported layer; the structure comprises a substrate and a buffer layer on the substrate, the buffer layer constituting the layer based on nitrides of elements III, the entire surface of which is continuously covered by a crystalline passivation layer; The buffer layer has a thickness of between 10 and 200 nm; the substrate is based on silicon and the buffer layer comprises a layer of aluminum nitride AlN and in addition a layer of gallium nitride and aluminum Al 'GaN on the aluminum nitride layer AlN; the structure comprises a substrate based on sapphire A1203, silicon Si, silicon on insulator SOI, silicon carbide SiC, aluminum nitride AlN, zinc oxide ZnO or gallium arsenide GaAs.
    [0005] BRIEF DESCRIPTION OF THE DRAWINGS Other advantages and characteristics of the process according to the invention and of the associated product will become more apparent from the following description of several variant embodiments, given by way of non-limiting examples, from the accompanying drawings on which: - Figure 1 illustrates an example of a method of manufacturing a semiconductor structure based on element III nitrides; FIG. 2 schematically illustrates an example of a product obtained by implementing the method illustrated in FIG. 1; FIGS. 3 and 4 illustrate two diffraction images in the crystallographic directions [1-100] and [1-210], respectively, a crystalline passivation layer according to the invention, - Figure 5 illustrates a support having a mesa structure, and - Figure 6 illustrates a support having a box structure.
    [0006] In the different figures, the same references designate similar elements. DETAILED DESCRIPTION OF THE INVENTION The invention relates to the passivation of a semiconductor structure by means of a crystalline passivation layer covering the entire surface of a nitride-based layer of elements III of said structure. . This crystalline passivation layer is deposited on said surface from silicon atoms, and has silicon atoms bonded to the surface of the nitride-based layer of elements III and arranged in a periodic arrangement so that a diffraction pattern of said crystalline passivation layer obtained by graft incidence electron diffraction in the [1-100] direction comprises: - a central line (0, 0) and whole order lines (0, -1) and (0, 1), two diffraction lines of non-integer order (0, -1/3) and (0, -2/3) between the central line (0, 0) and the order line integer (0, -1), and - two diffraction lines of non-integer order (0, 1/3) and (0, 2/3) between the central line (0, 0) and the order line integer (0, 1).
    [0007] Such a diffraction pattern corresponds to a hexagonal periodic arrangement rotated 300 with respect to the network of the III nitride-based layer and with a mesh parameter 13 times greater than the mesh parameter of the base layer. of nitride of elements III.
    [0008] The layer based on element III nitrides can be a thick layer ("template" in English) or self-supported said bulk substrate ("bulk substrate" in English), in which case it constitutes the semiconductor structure. The semiconductor structure based on element III nitride can thus be a GaN, AlN, etc thick layer, or a solid GaN, AlN, etc. substrate, or else an epitaxial structure (epiwafer in English). . It can also be supported by a substrate and a buffer layer. The following description will be made with reference to this configuration. It can thus for example have a light emitting diode configuration, of high electron mobility transistor (HEMT of the English "high electron mobility transistor"). FIG. 1 illustrates an alternative embodiment of the method according to the invention. The method comprises the steps of: forming a buffer layer on a substrate, said layer comprising an element III nitride layer; depositing a crystalline passivation layer on the buffer layer. Substrate To manufacture the semiconductor structure, a substrate 10 is used on which different deposition steps are carried out.
    [0009] The substrate 10 used may be A1203 sapphire, silicon Si, silicon carbide SiC, aluminum nitride AlN, or zinc oxide ZnO or gallium arsenide GaAs. In one embodiment, the substrate is silicon.
    [0010] The use of a silicon substrate has many advantages over the use of a sapphire substrate; in particular: a silicon substrate is less expensive than a sapphire substrate; the dimensions of the silicon substrates (generally up to 12 inches, ie 30.48 cm) are larger than those of the sapphire substrates (generally up to 6 inches, ie 15.24 cm); it is therefore possible to manufacture a GaN gallium nitride layer of larger surface area using a silicon substrate; the different stages of manufacturing the post-growth components (rear-face polishing, front-face transfer, removal of the substrate, etc.) after the growth of the gallium nitride GaN layer are simpler and less expensive in the case of use of a silicon substrate only in the case of a sapphire substrate. Thus, the use of silicon substrates makes it possible, for example, to manufacture light-emitting diodes (LEDs) at low production cost, which can be particularly advantageous in the field of lighting. Advantageously, the substrate 10 may be a patterned substrate comprising a mesa structure 11 in the form of a raised plate (the size of which may vary from 10 × 10 μm to 400 × 400 μm) and obtained by etching the surface of the substrate surrounding the plate. , as illustrated in FIG. 5, or else a box structure, as represented in FIG. 6, in which the element III nitride buffer layer 20, in this case made of AlN and AlGaN, and the layer In another embodiment, a method of manufacturing the patterns, such as partial masking of the surface by a mask of dielectric materials, can be advantageously used.
    [0011] The use of such a patterned substrate makes it possible to limit the cracking of the layer of epitaxial gallium nitride on the substrate 10, and thus to increase the critical thickness of gallium nitride GaN that can be deposited on the substrate. substrate 10 without creating cracks.
    [0012] For example, it is possible to produce an uncracked layer of gallium nitride GaN with a thickness of 5 μm using a substrate including a mesa structure of 200 × 200 μm, whereas the use of an unstructured substrate makes it possible to produce only one layer. uncracked gallium nitride GaN thickness 1 μm.
    [0013] Formation of the Buffer Layer The method comprises a step 100 for forming a buffer layer 20, whose means by means of which the upper layer constitutes the nitride-based layer of elements III on which the crystalline passivation layer 31 will be deposited. buffer layer may comprise an aluminum nitride AlN layer, AlGaN aluminum gallium nitride, AlGaBN aluminum gallium boron nitride, AlN / AlGaN stack, AlGaN zinc ZnO, BN boron nitride or silicon carbide SiC. However, in all cases, the buffer layer has a top layer based on element III nitrides, such as aluminum nitride AlN, AlGaN aluminum gallium nitride. In the case of the present example, this forming step 100 comprises the deposition 110 of a layer 21 of aluminum nitride AIN. The formation of a buffer layer 20 including a layer 21 of aluminum nitride AIN makes it possible to improve the quality of the subsequently deposited layer of gallium nitride GaN. For example, when the substrate 10 used is silicon Si, the direct growth of gallium nitride GaN on silicon Si is very difficult due in particular to the high chemical reactivity between gallium Ga and silicon Si at high temperature. The formation of a buffer layer 20 including a layer 21 of aluminum nitride AIN makes it possible to remedy these difficulties, and therefore to improve the quality of the subsequently epitaxially grown GaN nitride layer.
    [0014] The buffer layer 20 may have a thickness of between 10 nm and 500 nm, preferably between 50 nm and 200 nm. A buffer layer with a thickness greater than 200 nm makes it possible to obtain a good crystalline quality of the buffer layer 20, and therefore to improve that of the epitaxially-grown III nitride layer. The crystalline passivation layer according to the invention, which completely covers the buffer layer, however, makes it possible to ensure a good crystalline quality of the epitaxially grown III nitride layer, even if the crystalline quality of the buffer layer is not sufficient. Max. Therefore, it is not necessary for the buffer layer 20 to reach a thickness greater than 200 nm. Thus, preferably, the buffer layer 20 has a thickness of between 10 and 200 nm, or even between 50 and 100 nm. The fact of limiting the thickness of the buffer layer 20 below 200 nm advantageously makes it possible to reduce the duration of the process, since the growth time of a layer 21 of aluminum nitride AIN is relatively long. Another advantage is the fact that with a thin buffer layer 20, which is completely covered by a crystalline passivation layer, the problem of dislocations in this buffer layer solved by the crystalline passivation layer is it is resolved faster, preventing dislocations from spreading and causing dislocations. The formation step 100 of the buffer layer 20 may also comprise an optional step 120 of depositing a layer 22 of aluminum nitride and gallium AlGaN on the aluminum nitride layer 21 AIN. This provides a complex buffer layer of aluminum nitride AlN and AlGaN aluminum gallium nitride. The AlGaN aluminum gallium nitride layer 22 makes it possible to reduce the dislocation density of the layer on which the crystalline passivation layer is deposited. Advantageously, the thickness of the buffer layer 20, and therefore the sum of the thicknesses of the layers 21, 22 of aluminum nitride AIN and of aluminum and gallium AlGaN nitride can be between 10 nm and 500 nm, and of preferably between 50 and 200 nm, with for example the following distribution: - 25-100 nm of aluminum nitride AlN, - 25-400 nm of AlGaN aluminum and gallium nitride.
    [0015] This makes it possible to reduce the growth time of the buffer layer while benefiting from the advantages relating to the deposition of aluminum nitride and aluminum and gallium nitride layers.
    [0016] Preferably, the surface of the buffer layer, i.e., the surface of the element III nitride layer, on which the crystalline passivation layer will be deposited, is formed as smooth as possible. Deposition of a Crystalline Passivation Layer The process comprises a step of depositing a crystalline passivation layer 31 on the buffer layer 20. This deposition of a crystalline passivation layer 31 is for example obtained by exposing the surface of the buffer layer 20 to a precursor containing silicon Si atoms. The precursor containing silicon atoms may for example be SiH 4 silane, Si 2 H 6 disilane, or SiH (CH 3) 3 timethylsilane. Deposition can also be achieved by combining the silicon atoms with a stream of nitrogen atoms obtained, for example, from NH 3 ammonia molecules.
    [0017] The step of depositing the crystalline passivation layer 31 corresponds to a surface treatment which leads to a surface reconstruction of the atoms deposited on the surface of the buffer layer 20.
    [0018] Indeed, following the exposure of the surface of the buffer layer 20 to the Si silicon atoms and possibly to the nitrogen atoms, silicon Si atoms bind to the surface of the buffer layer by creating a hexagonal periodic arrangement turned 30 ° relative to the network of the III nitride-based layer on which the atoms are deposited and with a mesh parameter V times greater than that of the element III nitride-based layer. The formation of this surface reconstruction is measurable by electron diffraction techniques and its coverage rate of the surface can be quantified by recording the intensity of diffraction lines specific to this surface reconstruction. Electron diffraction is a technique used to study matter by bombarding a sample with electrons and observing the resulting diffraction pattern.
    [0019] An example of an electron diffraction technique that can be used in the context of the present invention to study the formation of the crystalline layer during the deposition phase is the high energy electron diffraction ("reflection high energy electron diffraction"). RHEED), which is a technique for determining the crystalline structure of the surface in an ultra-empty environment. In particular, the RHEED technique makes it possible to determine the reconstruction of the surface, to measure the speed of growth and to qualitatively assess the flatness of the surface. A RHEED device consists of an electron gun that creates a monocinetic electron beam with an energy of 10 to 50 keV focused on the surface. The wavelength associated with the electrons is of the order of 0.1 A. The beam reaches the grazing incidence surface at an angle of 1 to 2 degrees. In this configuration the interaction of electrons with the surface is limited to a few atomic planes. The electrons reflected and diffracted by the atoms of the surface are collected on a fluorescent screen which makes it possible to visualize the corresponding diffraction pattern and this photograph can then be digitized using a CCD camera. The "Reflection High Energy Electron Diffraction" document, by Ayahiko Ichimiya and Philip I. Cohen, Cambridge University Press, 2004, describes this technique. With reference to FIGS. 3 and 4, two diffraction images of the crystalline layer are illustrated in the respective crystallographic directions [1-100] and [1-210]. In FIG. 4, the diffraction pattern of the crystalline layer in the direction [1210] comprises only whole-order diffraction lines: a central line (0.0) 42 and two integer lines (0, -1) 43 and (0, 1) 44 on either side of said central line 42. Thus there are no lines of non-integer order between the lines of integer order (0, -1 ) and (0, 1) and the central line (0, 0). It should be noted that the spacing between whole-order diffraction lines is inversely proportional to the mesh parameter in the plane of the surface. In FIG. 3, however, corresponding to the diffraction pattern of the crystalline layer in the [1-100] direction, the presence of a surface reconstruction leads to the presence of additional fractional lines. that is to say of non-integer order, in this case of 1/3 order characteristic of a reconstruction called 1x3. The diffraction pattern of the crystalline layer in the [1-100] direction thus comprises: - a central line (0, 0) and lines of integer order (0, -1) and (0, 1), - two non-integer order diffraction lines 31, say (0, -1 / 3) and (0, -2/3), between the lines (0, 0) 32 and (0, -1) 33, and two non-integer order diffraction lines 35, say (0, 1/3) and (0, 2/3), between the lines (0, 0) 32 and (0, 1) 34. Therefore, the diffraction pattern in the [1-210] direction having only a space between the whole order lines, whereas the diffraction pattern in the [1-100] direction having three spaces between the lines of entire order, that is why this crystalline layer is called 1x3. Thus, and contrary to the methods of the prior art comprising a step of deposition of a nanoporous SiNx layer whose structure and exact composition are unknown, the method according to the invention proposes the deposition of a crystalline layer of so-called passivation 1x3 of structure and composition perfectly defined, and whose pore density is preferably the lowest possible, or substantially zero.
    [0020] In fact, in the methods of the state of the art, it is sought to avoid a total coverage rate of the surface of the nitride-based layer III. However, the inventors have discovered that the dislocation density is minimal when the crystalline layer covers the entire surface of the element III nitride-based layer.
    [0021] The deposition of the 1x3 passivation crystal layer induces a passivation of the surface of the buffer layer 20. This passivation makes it possible to render the buffer layer 20 inert with respect to exposure to the air and thus to prevent any oxidation reaction. Moreover, exposure to the air of a semiconductor structure having such a 1x3 passivation crystal layer on its element III nitride top layer does not alter the 1x3 surface reconstruction of said crystalline layer. passivation 1x3.
    [0022] In order for the passivation by the crystalline passivation layer 31 to provide good protection for the III-based nitride-based layer on the surface of which it is deposited, the crystalline passivation layer 31 covers the entire surface of this layer. based on nitride III elements continuously, that is to say in the absence of holes or openings contrary to what is sought by those skilled in the art during the manufacture of a micro-nanoporous SiNx layer. In this respect, it should be noted that the crystalline passivation layer 31 has a very small thickness, of the order of one monolayer of silicon atoms, ie of the order of 2 A to 3 A. In fact, in order to preserve the crystalline character of the passivation layer, the thickness thereof is preferably less than 6 A. Obtaining a support for the growth of nitrides of elements III at the end of the deposition step 201 of the passivation crystal layer 31, a support is obtained for the growth of a semiconductor structure based on element III nitrides, such as a gallium nitride GaN layer. Growth techniques used The deposition step of the crystalline passivation layer 31 can consist of ultra-vacuum deposition. Advantageously, the steps of: - formation of the buffer layer 20, and / or deposition of the crystalline passivation layer 31 on the buffer layer 20, can be carried out by molecular beam epitaxy EJM (or "MBE" acronym "molecular beam epitaxy"), which is realized in an ultra-empty environment. It is also possible that the deposition step of the crystallization passivation layer 31 consists of a vapor phase deposition, more precisely a vapor phase epitaxy deposition with EPVOM organometallic compounds (or "MOVPE"), the acronym for the expression Saxon "Metalorganic vapor phase epitaxy"). The fact of forming the buffer layer by molecular beam epitaxy - and therefore in an ultrahigh vacuum environment - has many advantages over organometallic vapor phase epitaxy buffer layer formation techniques. In particular, the formation of the buffer layer 20 by molecular beam epitaxy makes it possible, on the one hand, to eliminate any trace of reactive gas in the environment of the substrate, and thus to limit the risks of parasitic reaction of nitriding of the substrate. surface of the substrate, - secondly to limit the fouling of the growth reactor and thus improve the manufacturing efficiency by reducing the frequency of maintenance operations of the reactor. In addition, the formation of the buffer layer 20 by molecular beam epitaxy makes it possible to obtain a surface of the element III nitride layer which is very smooth, thus improving the formation of the crystalline passivation layer 31. On the other hand, the use of ultraviolet in MBE also makes it possible to follow in situ - for example by electron diffraction - the deposition of the crystalline layer. This allows precise monitoring of the deposition step of the crystalline layer so as to stop this step when the crystalline layer totally covers the surface.
    [0023] Thus, the method may comprise a step of measuring the coverage rate of the passivation crystalline layer 31 by electron diffraction at grazing incidence in the direction [1-100] during the step of depositing the crystalline passivation layer 31 so as to obtain a diffraction pattern of said crystalline passivation layer, wherein the duration of the step of depositing the crystalline passivation layer is related to the intensity of at least one diffraction line of an image of diffraction of the crystal passivation layer obtained by electron diffraction in the crystallographic direction [1-100].
    [0024] As indicated above, the diffraction pattern of the crystalline passivation layer 31 in the [1-100] direction then comprises: a central line (0, 0) and integer lines (0, -1) and (0, 1), - two non-integer (0, -1/3) and (0, -2/3) diffraction lines between the central line (0, 0) and the integer line (0, -1), and - two non-integer (0, 1/3) and (0, 2/3) diffraction lines between the central line (0, 0) and the integer line (0, 1). Preferably, the step of depositing the crystalline passivation layer 31 is interrupted when the luminous intensity of the non-integer order intermediate lines of the diffraction image (in the crystallographic direction [1-100]) is maximum which corresponds to a complete coverage rate of the surface of the element III nitride layer by the crystalline passivation layer 31. This maximum intensity is easily identifiable. In fact, by using a CCD camera, it is sufficient to record the intensity profile of one of the non-integer order diffraction lines in the direction [1-100] as a function of the deposition time of the film layer. passivation. At first, the diffraction line of non-integer order appears then its intensity increases during the deposition, to arrive at a step before in a second time to decrease and not to disappear. The maximum intensity is therefore detectable by the stability of this intensity, which can last several minutes. A semiconductor structure thus passivated can therefore be exposed to air, stored or manipulated without degradation of its surface and retaining its specific properties leading to a three-dimensional growth mode. Subsequent growth of an III element nitride layer can be readily resumed on such a passivation layer. Such a structure is termed "epi-ready" to signify that epitaxy can be undertaken on said structure without having to chemically prepare the surface beforehand.
    [0025] Example of a Manufacturing Process An example of a method according to the invention will now be described. The silicon substrate used has a crystallographic orientation (111). An aluminum nitride buffer layer is formed on the silicon substrate by molecular beam epitaxy. The formation of the buffer layer is interrupted when the thickness thereof is between 10 and 200 nm. The step of depositing the 1x3 crystalline layer is then carried out. A treatment of the surface of the buffer layer by molecular beam epitaxy is carried out using silicon atoms and NH 3 ammonia molecules. This surface treatment leads to the formation of a new crystal structure that is well defined, measurable and identifiable by electron diffraction. During the deposition of the crystalline layer, the surface is observed by an electron diffraction technique of grazing incidence delivery of a monocinetic electron beam to the crystalline layer being formed to observe the resulting diffraction pattern ( following the crystallographic direction [1-100]). The ordered periodic structure of the 1x3 crystal layer makes it possible to diffract the electrons and thus obtain a specific diffraction image. The duration of the crystalline layer deposition step is a function of the intensity of the non-integer order diffraction lines observed on the diffraction pattern.
    [0026] In particular, the step of depositing the crystalline layer is interrupted when the intensity of at least one of the diffraction lines observed in the diffraction pattern is maximum, which is detectable by the stability of this intensity.
    [0027] An element III nitride semiconductor structure is thus obtained comprising a III element-based nitride buffer layer, the entire surface of which is completely covered by a crystalline passivation layer comprising silicon atoms bonded to the surface and arranged in a periodic arrangement so that the diffraction pattern of the crystalline layer in the [1-100] direction comprises: - a central line (0, 0) and lines of integer order (0, - 1) and (0, 1), two non-integer order diffraction lines (0, -1/3) and (0, -2/3) between the central line (0, 0) and the line of integer order (0, -1), and - two diffraction lines of non-integer order (0, 1/3) and (0, 2/3) between the central line (0, 0) and the order line integer (0, 1). This corresponds to a periodic hexagonal arrangement rotated 300 with respect to the network of the element III nitride-based layer and with a mesh parameter V times greater than the mesh parameter of said zonitride-based layer. elements III. Those skilled in the art will have understood that many modifications can be made to the process described above without physically going out of the new teachings presented here. For example, the steps of forming the buffer layer and depositing the crystalline layer can be performed by EPVOM. In addition, the growth step of the element III nitride semiconductor structure can be carried out by EJM.
    [0028] It is therefore obvious that the examples which have just been given are only particular illustrations that are in no way limitative.
    权利要求:
    Claims (23)
    [0001]
    REVENDICATIONS1. A method of manufacturing a semiconductor structure, characterized in that the method comprises a step of depositing (201) a crystalline passivation layer (31) covering the entire surface of a nitride-based layer. III elements of the semiconductor structure, said crystalline passivation layer being deposited from a precursor containing silicon atoms and said crystalline passivation layer (31) consisting of silicon atoms bonded to the surface of the nitride-based layer of elements III and having a triple periodicity of silicon atoms in the crystallographic direction [1-100] so that a diffraction image of said crystal passivation layer obtained by electron diffraction in incidence grazing in the direction [1-100] comprises: - a central line (0, 0) and lines of integer order (0, -1) and (0, 1), - two diffraction lines of non-order integer (0, -1/3) and ( 0, -2/3) between the central line (0, 0) and the line of integer order (0, -1), and - two diffraction lines of non-integer order (0, 1/3) and (0, 2/3) between the central line (0, 0) and the line of integer order (0, 1).
    [0002]
    2. Method according to the preceding claim, wherein the crystalline passivation layer has a simple periodicity in the crystallographic direction [1-210] so that a diffraction image of said crystal passivation layer obtained by electron diffraction incidence. grazing in the direction [1-210] comprises a central line (0, 0) and lines of integer order (0, -1) and (0, 1) without lines of non-integer order between them.
    [0003]
    3. Method according to one of the preceding claims, wherein said crystalline passivation layer consists of silicon atoms bonded to the surface of the nitride-based layer III and arranged in a hexagonal periodic arrangement rotated 30 ° with respect to the network of the nitride layer of elements III and with a mesh parameter V times greater than the mesh parameter of the network of the element III nitride-based layer.
    [0004]
    4. Method according to one of the preceding claims, wherein the step of depositing the crystalline layer of passivation consists of a deposit under ultra-vacuum.
    [0005]
    5. Method according to the preceding claim, wherein the step of depositing the crystalline passivation layer consists of a deposition by molecular beam epitaxy.
    [0006]
    6. Method according to the preceding claim, comprising a step of measuring the coverage rate of the crystalline layer of passivation by electron diffraction grazing incidence in the direction [1-100] during the deposition step of the crystalline layer of passivation so as to obtain a diffraction pattern of said crystalline passivation layer, wherein the duration of the step of depositing the crystalline passivation layer is a function of the intensity of at least one non-order diffraction line of a diffraction pattern of the crystalline passivation layer obtained by electron diffraction in the crystallographic direction [1-100]. 15
    [0007]
    7. Method according to the preceding claim, wherein the diffraction pattern of the crystal layer in the direction [1-100] comprises: - a central line (0, 0) and lines of integer order (0, -1) ) and (0, 1), two non-integer (0, -1/3) and (0, -2/3) diffraction lines between the central zero line (0, 0) and the d-line integer order (0, -1), and - two non-integer (0, 1/3) and (0, 2/3) order diffraction lines between the central line (0, 0) and the d-line integer order (0, 1). the step of depositing the crystalline passivation layer being interrupted when the light intensity of said non-integer order lines is maximum. 25
    [0008]
    8. Method according to one of claims 1 to 3, wherein the step of depositing the crystalline passivation layer consists of a vapor deposition.
    [0009]
    9. The process according to the preceding claim, wherein the step of depositing the crystalline passivation layer consists of an organometallic vapor phase deposition.
    [0010]
    10. The process as claimed in any one of the preceding claims, in which the crystalline passivation layer has a thickness of less than 6 A.
    [0011]
    A method according to any one of the preceding claims comprising a step of forming (100) on a substrate (10) a buffer layer (20), said buffer layer (20) comprising the nitride-based layer (20). elements III on which is deposited the crystalline layer of passivation (31).
    [0012]
    12. Method according to the preceding claim, wherein the buffer layer (20) has, at the end of its formation, a thickness of between 10 and 200 nm.
    [0013]
    The method according to one of claims 11 to 12, wherein the substrate is silicon-based and the step (100) of forming the buffer layer (20) includes depositing (110) a nitride layer. AIN aluminum (21).
    [0014]
    The method according to the preceding claim, wherein the step of forming (100) the buffer layer (20) includes depositing (120) a layer of AlGaN gallium aluminum nitride (22) on the layer of aluminum nitride.
    [0015]
    15. Element III nitride semiconductor structure comprising a III-nitride-based layer all of whose surface is totally covered by a crystalline passivation layer (31) consisting of silicon bound to the surface and having a triple periodicity of silicon atoms in the crystallographic direction [1-100] such that a diffraction pattern of said crystalline passivation layer obtained by electron diffraction grazing incidence in the direction [1-100] comprises: - a central line (0, 0) and lines of integer order (0, -1) and (0, 1), - two non-integer order diffraction lines (0 , -1/3) and (0, -2/3) between the central line (0, 0) and the integer line (0, -1), and - two non-integer order diffraction lines (0, 1/3) and (0, 2/3) between the central line (0, 0) and the line of integer order (0, 1). 30
    [0016]
    16. Structure according to the preceding claim, wherein the crystalline layer has a simple periodicity in the crystallographic direction [1-210] so that a diffraction image of said crystalline passivation layer obtained by electron diffraction grazing incidence following the direction [1-210] has a central line (0, 0) and lines of integer order (0, -1) and (0, 1) without any non-integer order lines therebetween.
    [0017]
    17. Structure according to one of claims 15 or 16, wherein said crystalline passivation layer consists of silicon atoms bonded to the surface of the layer based on element III nitrides and arranged in a hexagonal periodic arrangement turned 300 with respect to the network of the element III nitride-based layer and with a mesh parameter V times larger than the mesh parameter of the element III nitride layer network.
    [0018]
    18. Structure according to one of claims 15 to 17, wherein the crystalline passivation layer has a thickness of less than 6 A.
    [0019]
    19. Structure according to one of claims 15 to 18, wherein the III nitride-based layer is a self-supported layer.
    [0020]
    20. Structure according to one of claims 15 to 18, comprising a substrate (10) and a buffer layer (20) on the substrate, the buffer layer constituting the layer based on element III nitrides, the entire surface of which is continuously covered by a crystalline passivation layer (31).
    [0021]
    21. Structure according to the preceding claim, wherein the buffer layer (20) has a thickness of between 10 and 200 nm.
    [0022]
    22. Structure according to one of claims 20 to 21, wherein the substrate (10) is based on silicon and the buffer layer comprises a layer of aluminum nitride AlN (21) and furthermore a layer of gallium nitride and AlGaN aluminum (22) on the aluminum nitride AlN layer (21).
    [0023]
    23. Structure according to one of claims 15 to 21, comprising a substrate (10) and wherein the substrate is based on sapphire, silicon Si, silicon on insulator SOI, silicon carbide SiC, nitride. aluminum AlN, zinc oxide ZnO or GaAs gallium arsenide.
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    同族专利:
    公开号 | 公开日
    CN107408492A|2017-11-28|
    CN107408492B|2020-10-16|
    JP2018509754A|2018-04-05|
    KR20170105598A|2017-09-19|
    EP3248212A1|2017-11-29|
    US20180012753A1|2018-01-11|
    JP6684812B2|2020-04-22|
    FR3031833B1|2018-10-05|
    WO2016116713A1|2016-07-28|
    EP3248212B1|2021-08-18|
    US10361077B2|2019-07-23|
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    优先权:
    申请号 | 申请日 | 专利标题
    FR1550461|2015-01-21|
    FR1550461A|FR3031833B1|2015-01-21|2015-01-21|PROCESS FOR MANUFACTURING A PASSIVE ELEMENTS III-BASED NITRIDE SEMICONDUCTOR STRUCTURE AND SUCH A STRUCTURE|FR1550461A| FR3031833B1|2015-01-21|2015-01-21|PROCESS FOR MANUFACTURING A PASSIVE ELEMENTS III-BASED NITRIDE SEMICONDUCTOR STRUCTURE AND SUCH A STRUCTURE|
    US15/545,289| US10361077B2|2015-01-21|2016-01-21|Method for producing a passivated semiconductor structure based on group III nitrides, and one such structure|
    PCT/FR2016/050124| WO2016116713A1|2015-01-21|2016-01-21|Method for producing a passivated semiconductor structure based on group iii nitrides, and one such structure|
    KR1020177023093A| KR20170105598A|2015-01-21|2016-01-21|METHOD FOR MANUFACTURING A III-NITRIDE-BASED PASSED SEMICONDUCTOR STRUCTURE AND PROGRAM|
    JP2017538726A| JP6684812B2|2015-01-21|2016-01-21|Method for making passivated semiconductor structures based on group III-nitrides and such structures|
    CN201680013729.XA| CN107408492B|2015-01-21|2016-01-21|Method for producing a passivated semiconductor structure based on a group III nitride and such a structure|
    EP16705569.8A| EP3248212B1|2015-01-21|2016-01-21|Method for producing a passivated semiconductor structure based on group iii nitrides, and one such structure|
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